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Analog dot product Engine Acceleration utilizing multi-input memristor array for Machine Learning and Optimization Applications

Implementing Organization

Indian Institute Of Technology, Gandhinagar
Principal Investigator
Dr. Sandip Lashkare
Indian Institute Of Technology, Gandhinagar, Gujarat
sandip.lashkare@iitgn.ac.in
CO-Principal Investigator
Nil

Project Overview

In the era of big data, AI/ML algorithms are essential for accelerating computation and are widely used in consumer electronics, industrial, and healthcare sectors. A key operation enabling these technologies is vector-matrix multiplication (VMM). While GPUs and TPUs have been used to enhance VMM, the Von-Neumann bottleneck—separating memory and computation—causes energy inefficiency and latency. In-memory computing (IMC) attempts to solve this problem by performing computations within memory akin to human brain, reducing both energy consumption and latency. Memristor crossbar arrays have shown potential for IMC due to their simple architecture, high density, and efficiency in analog dot product operations. These arrays utilize Ohm’s law and Kirchhoff’s current law to perform multiplication and accumulation directly. Current efforts to improve hardware accelerators focus on enhancing memory performance, algorithms, and circuit designs. However, limitations like restricted input terminals to memory arrays hinder performance, requiring either larger arrays or time-multiplexing, which increase cost or reduce speed. Three main areas are now being worked on in order to speed up computing: developing innovative circuit topologies, improving memristor materials, and creating various algorithm optimisation techniques. However, by only taking one input at a time, the conventional 2-terminal memristor creates a bottleneck that restricts parallel processing. One of the biggest challenges is to develop memory devices with multiple inputs without increasing the chip area. The proposed solution is a multi-input memristor that can handle multiple inputs at once, beginning with a three-terminal design. This way there can be a great improvement in terms of area efficiency (nX) and speed increase (2X). A solution to improve the memory array performance by adding multiple inputs to the memory device without compromising on area while accelerating speed is the tremendous challenge in the memory community in academia and industry across the globe. Further, many AI/ML and circuit community in the country heavily depends on the memory system imported from outside the country for research or for prototype of their products. Hence, self-reliance on such memory systems will be highly beneficial to the nation. This project aims to create a proof-of-concept system, including: A 3-terminal memristor array system via integration with an FPGA-based control system for operation. Further, the FPGA system also need not be procured from outside of the country. The industries like Vicharak in the country are in the phase of launching Vaaman Single Board Computer which has integrated FPGA and Processor. Hence, realizing complete system having all components made in the country would be a significant achievement. This is also in-line with the India semiconductor mission to push electronic manufacturing in India.
Funding Organization
Quick Information
Area of Research
Engineering Sciences
Focus Area
Electrical, Electronics & Computer Engineering
Start Date
27 Mar 2025
End Date
26 Mar 2028
Status
ongoing
Output
No. of Research Paper
00
Technologies (If Any)
00
No. of PhD Produced
00
Publications
01
No. of Patents
Filed : 00
Grant : 00
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