Efficient FPGA-based Hardware Accelerator for Homomorphic Encryption-based Secure and Encrypted Machine Learning Architecture
Implementing Organization
Indian Institute Of Technology Kanpur
Principal Investigator
Dr. Debapriya BasuRoy
Indian Institute Of Technology Kanpur
dbroy@cse.iitk.ac.in
CO-Principal Investigator
Dr. Urbi Chatterjee
Indian Institute Of Technology Kanpur, Kanpur Iit, Po Kanpur,Uttar Pradesh,Kanpur Nagar-208016
Project Overview
The recent growth in machine learning (ML) and artificial intelligence (AI) has transformed multiple domains like healthcare, agriculture, transport, and bioinformatics. ML and AI enable us to automatically learn about any system from prior experience rather than explicit programming. Therefore, ML and AI can be used to train machines to solve complex problems like image classification, weather predictions, and genome sequencing. But applying ML and AI algorithms to these problems requires efficient, high-speed processing that often can not be provided by a conventional workstation. Therefore, cloud-based accelerated ML services are deployed to govern such complex and resource-intensive algorithms. This solves the efficiency issue but raises the question of security and privacy. Applications like finance and healthcare handle lots of sensitive data, and maintaining the confidentiality and integrity of that data is of paramount importance. Homomorphic encryption allows the user to execute arithmetic operations like addition and multiplication in the encrypted domain. Therefore, if one can develop a ML architecture that operates on the encrypted data and produces encrypted result using homomorphic encryption, the concern regarding the confidentiality and integrity can be resolved. Researchers have exactly done that by using Microsoft’s simply encrypted arithmetic library (SEAL). In 2009, the researchers first showed the possibility of constructing fully homomorphic encryption (FHE) with an unlimited number of encrypted additions and multiplications, which was later improved by schemes like BGV (Brakerski-Gentry-Vaikuntanathan), BFV (Brakerski-Fan-Vercauteren), and GSW (Gentry-Sahai-Waters). The current schemes like TFHE (Fast Fully Homomorphic Encryption over the Torus) shows how to develop encrypted logic gates like AND, OR, NOT, and CKKS (Cheon-Kim-Kim-Song) is tailored specifically for approximate arithmetic on real and complex numbers. We have performed a feasibility study of applying different ML methodologies (logistical regression, decision tree, neural network, etc.) and have found that CKKS and TFHE perform better in terms of efficiency and latency compared to other FHE schemes. CKKS and TFHE both use lattice-based cryptography that involves computationally intensive polynomial arithmetic. Thus, executions of such algorithms on software involve large latency and, henceforth, can not compete with standard ML algorithms working on unencrypted data. This proposal aims to design a hardware-centric approach for homomorphic encryption schemes CKKS and TFHE, with the focus on accelerating encrypted machine learning inference. The aim is to create an end-to-end hardware pipeline for time-critical operations like number-theoretic-transform (NTT), modular reduction, relinearization, key-switching, and bootstrapping that would evolve the current state of hardware-accelerated FHE to work in real-time with a significantly low latency. The main deliverables of this proposal are listed below: 1. The first objective of this project is to create efficient hardware modules for different components that are used in homomorphic encryptions like TFHE and CKKS. We will develop an automated HDL code generator that can generate different hardware modules (NTT, Hash) for different homomorphic encryption algorithms with varying noise budget and parameters. 2. Using the developed hardware modules, we will develop three different levels of FHE processors, each with varying overhead, flexibility, and efficiency, supporting both TFHE and CKKS. The processors will be used to accelerate encrypted machine learning modules like logistical regression, decision tree, support vector machine (SVM), and convolutional neural network (CNN). The developed hardware-accelerated FHE processors will be prototyped on AMD-Xilinx Zynq Ultrascale and Versel AI-Engine based FPGAs.