Research Projects

Transistors downscaling encourages monolithic 3D (M3D) integration, which is a multilayer stack of logic, sensors, or memory devices. It requires low-temperature processes (less than 400 °C) to preserve underlying devices. Conventional silicon (Si) technologies face fundamental limitations in such architectures due to their high thermal budget. Oxide semiconductors (OS) emerge as promising candidates for various applications, from displays to memory, sensors, and neuromorphic systems, as these offer low thermal budget, CMOS-compatible process, and reasonable mobility. In active-matrix flat-panel displays (FPDs), OS-based thin film transistors (TFTs) serve as backplane drivers, which supply a constant current to the organic light-emitting diodes (LEDs) during the emission stage. However, these TFTs suffer from variation in threshold voltage (VT) and carrier mobility, leading to current variations between individual pixel elements and uneven brightness over display screens. These variabilities are balanced by employing self-compensating circuits at the backplane, which increase the transistor count, pixel area, and cost with reduced scalability. This project aims to provide an energy-efficient, low-voltage, variation-resilient, compact circuit design. It is based on the hypothesis that integrating OS-based ferroelectric-TFTs (FE-TFTs) at the backplane, implying a varying pulse width/amplitude method, will dynamically control polarization charges. This capability allows dynamic VT control and supports non-volatile memory functionality and synaptic behavior for neuromorphic computing applications. This work will also investigate other challenges, including limited erase operations for memory applications, low-frequency noise (LFN) behavior, and bias stress-induced instabilities, while accounting for fabrication-related issues. A comprehensive experimental and simulation-based approach is proposed to validate this hypothesis, which addresses materials, device circuit co-design, and long-term reliability concerns. Key experiments: (1) Fabrication of OS TFTs, metal-ferroelectric-metal/metal-ferroelectric-insulator-semiconductor (MFM/MFIS), and FE-TFTs: Utilizing techniques such as sputtering/atomic layer deposition (ALD) to deposit OS, FE, and IL films with post-deposition annealing (200-350°C, N₂, Ar, O₂, ambient for different times). Thin film characterization techniques (piezoresponse force microscopy and X-ray diffraction) will be used to characterize film properties. (2) Electrical characterization includes current-voltage (I-V), capacitance-voltage (C-V), polarization-voltage (P-V), and memory characteristics (endurance, retention). (3) Device calibration using physics-based TCAD models and LUT-based circuit simulation using the Cadence Virtuoso environment. This demands a vast range of exported data obtained from calibrated devices, which will further be used in the LUT to define a device symbol. (4) Noise behavior and reliability analysis: Characterization to evaluate LFN behavior, radiation, and bias stress-induced instabilities, impact device characteristics, and long-term reliability. (5) Fabrication of FE-TFT arrays (10x10) for multi-level states (16+, linearity greater than 0.95); further employed to simulate reservoir computing, which targets MNIST recognition with greater than 95% classification accuracy. The project leverages solution-processed FE for conductance modulation. Furthermore, integrating 3-tier M3D stacking IGZO/HZO will enable in-memory computing, addressing scalability via low-temperature processes (less than 350 °C). The successful completion of this project would lead to high-performance, cost-effective, and reliable display panels, flexible and wearable electronics, memory, and neuromorphic computing using OS-based transistors, addressing existing limitations. The project also aligns with India's current focus on electronics manufacturing, supported by MeitY, the Chips to Startup (C2S) program.