Research Projects

The ever-growing demand of increased data rate has fueled the research of high speed transceiver design. This has further been accelerated by the rapid growth in datacenter and cloud computing which require even more wireline communication at even higher speed. During transmission it is a common practice to serialise the data to reduce the requirements on number of channels needed which further increases the data rates and complicates the design of receiver. Further, at such high-speed the channel bandwidth is also limited and introduces several non-idealities such as inter symbol interference (ISI) thus requiring techniques such as equalization to successfully capture the transmitted signal. A simple high pass filter is used as an equalizer for data rates up to 10Gbps. However, when data rates start increasing beyond 10Gbps and also the channel loss start becoming more than 20dB then several different equalization schemes such as feed forward equalizer (FFE) and decision feedback equalizer (DFE) and a combination of theses are being used [7][8]. There are several different methods to perform the equalization such as the use of FIR filters either at transmitter or at receiver or at both to equalize the signal. The equalization at receiver is shown to be performed in an analog domain or in digital domain , or also in mixed signal domain. However, the rapid scaling of CMOS devices have made the realization of these complex equalizers in digital domain much easier using digital signal processing. This has motivated the circuit designers to explore the ADC based receivers to digitize the captured signal and perform equalization in digital domain [12]. The use of ADC in receiver chain allows the use of more spectrally efficient modulation schemes such as PAM-4 in transmission and thus paving the way for transmitting the data at much higher data rates ranging up to 56-112Gb/s. The challenge in ADC based receiver is to realize the high speed ADC with desired resolution in a power efficient manner. Further the, digital equalization at high data rate is also power consuming. It has been shown in that using a nonuniform quantization level within ADC can help in reducing the demand on required resolution of ADC for a given Bit-Error-Rate (BER). Recently there have been some work where researchers have attempted to embed the equalization within ADC architecture by incorporating equalization techniques, like Feedforward Equalisation(FFE) or Decision Feedback Equalization (DFE), directly within the analog-to-digital converter(ADC). Although this contrast with the earlier approach of using digital friendly technologyscaling to the use of realizing equalization in digital domain however, the use of equalisation within ADC helps in reducing the required resolution of ADC and thus optimize the power. It also helps in relaxing the equalization needed in digital domain. This work proposes to explore the use of time interleaved ADC with an embedded equalization to optimize the overall power efficiency. The use of time interleaving within ADC allows the use of poly-phase decomposition of FIR filters used to realize the equalizer and thus results in significant power saving. Further, this work attempts to explore a right balance of analog equalization and digital equalization to enhance the overall power efficiency.