Research Projects

The conventional neuromorphic hardware and neural network hardware accelerators are constrained by memory wall, high power consumption and limited throughput efficiency. The proposed project aims to develop energy-efficient and high-speed hardware accelerators for deep neural networks (DNNs) by leveraging neuromorphic and in-memory computing (IMC) techniques integrated with advanced spintronic devices such as STT-MRAM, SOT-MRAM, and domain wall motion (DWM) elements. These non-volatile spin devices offer fast switching, low power consumption, and high endurance, making them ideal for mimicking synaptic and neuronal behaviors in neuromorphic architectures and for performing vector-matrix multiplications directly within memory crossbar arrays. By co-designing device, circuit, and algorithm layers, the project will demonstrate compact and scalable DNN hardware accelerator capable of real-time learning and inference with significantly reduced energy and latency, especially suitable for edge AI applications. The project will target both conventional neural networks as well as spiking neural network architectures. A complete device-circuit-architecture workflow will be developed and impact of device variations and architectural optimization techniques on throughput efficiency will be evaluated. The outcomes include prototype architectures, benchmark results, toolchains for neural model mapping, and contributions to sustainable AI hardware development through publications, IP generation, and open-source tools. The project will pave path for solution to next generation neuromorphic hardware accelerators for applications like edge computing.