Research Projects

The advancement of computer architecture through innovations like out-of-order execution, branch prediction, and speculative execution has significantly enhanced performance of the system to a great extent and were agnostic about their secuity implications, until a couple of years back when the security researchers have uncovered several critical vulnerabilities namely spectre, meltdown and more which impacted the perception of security in general purpose systems. Most of the micro-architecture attacks are designed ad-hoc targeting each and every component of the micro-architecture shared across process boundaries and developing a realistic covert channel across them. The effect of multiple such constructs in the light of security is yet largely unexplored. In this research proposal we propose a thorough investigation of all of the components in architecture in light of security. Thus the task would be to systematically analyze all aspects of the security threats on such a platform. This would include the security analysis of each and every component of micro-architecture starting from the cache memory architecture, branch prediction unit, instruction prefetchers, out-of-order execution and speculative execution, re-order buffers, translational look-aside buffers and more. We would like to see the influence of these micro-architecture design choices using realistic micro-architecture simulators such as Gem5. In addition, this project aims to bridge the gap between the micro-architecture and the Instruction Set Architecture, and study the performance vs security tradeoff by finetuning each component structure. We thus largely focus on analyzing and mitigating micro-architectural vulnerabilities in RISC-V, a widely adopted open-source instruction set architecture (ISA). RISC-V’s transparency and modular design allow deep customization and analysis, but also make it a perfect platform to uncover unique threats. The project aims to deliver secure, indigenous hardware solutions tailored to address RISC-V’s vulnerabilities while balancing performance and efficiency. By leveraging open-source flexibility and rigorous security analysis, this research will advance the ecosystem of secure and trusted hardware and enable the safe adoption of RISC-V in critical and high-assurance applications.