Research Projects

Gallium Nitride (GaN) based power semiconductor devices are rapidly gaining popularity and research attention due to potential to improve efficiency, reduce form factor, increase drive currents and power handling capability, and increase frequency of operation of power electronic systems. Initial demonstrations in GaN technology has already shown promising performance figures in sub-600 V range. The push is now to maximize the performance output by enabling device operation up to the theoretically predicted limits and to extend the application base of the technology to beyond 600 V. However, the devices exhibiting best performance are still normally-on devices and far from the theoretically predicted figures. A reliable system operation and longer device lifetime, however, requires normally-off operation. Out of several approaches proposed to achieve normally-off operation in AlGaN/GaN HEMTs, pGaN gated and cascode HEMT technology have shown promise for a reliable operation. While cascode HEMT architecture carries advantage of retaining the excellent properties of a normally on device, its integration with a narrow band gap silicon-based device brings in its own limitations in terms of reduced overall breakdown voltage, increased sensitivity to temperature, increased interconnect parasitics, and limited understanding of the physical mechanisms governing device operation. On the other hand, pGaN gated architecture compromises on the overall current carrying capability of the device with a reduced gate control and brings in host of reliability challenges. The primary objective of the proposed work is to enable efficient and reliable normally off operation in these devices by developing fundamental insights into the physical mechanisms governing device behaviour and reliability. The approach to be adopted includes integration of experimental and computational techniques for a fast and cost-effective technology development cycle. A robust computational framework to accurately capture the dc as well as switching performance and reliability parameters of the device will be developed. The developed framework will then be used to design specialized test structures and setups to further probe into the device operation. A feedback between the experiments and computations will be used to probe into advanced reliability mechanisms. The expected output here is the identification of performance and reliability bottlenecks. Computations will then be used to carry out device design to address these bottlenecks and enable device design for even higher voltage nodes. The findings of this work are expected to provide novel insights into the operating principle and important reliability concerns in the device. Moreover, it will generate standardised techniques to implement performance and reliability tests and to capture them in a computational framework to benefit the research and industrial community at large to develop next generation technologies.