Research Projects

The implanted bioelectronics sector develops electronic devices for implantation in the body to treat, diagnose, or aid in recovery from a variety of medical illnesses. Cochlear implants, pacemakers, deep brain stimulators, spinal cord stimulators, and neural stimulators are used to treat chronic disorders and restore function. Such stimulator ICs require a stimulation unit with a digital processing unit. Keeping these stimulators safe from electrostatic discharge (ESD) incidents is a crucial design challenge. ESD events, induced by abrupt charge discharge between objects, produce voltage and current transients that can damage integrated circuits during handling or usage. Effective ESD protection is required to properly route these events to ground, so protecting the primary IC—particularly for implantable stimulator ICs, which contact directly with the body. Multi-channel stimulators (16 to 264 channels) necessitate separate ESD protection for each channel, resulting in large area overhead on the IC. Typically, conventional clamp circuit-based ESD protection is utilized to protect the IC. The ESD clamp typically includes a detecting block, a trigger circuit, and a MOSFET or SCR-based clamp, all of which take up a significant amount of chip surface. When scaled for all stimulator channels, the ESD area can exceed that of the core IC. Furthermore, some stimulators such as neurostimulator IC function at voltages of up to 10V for stimulation and 2.5V for signal detection. Thus, a compact custom multi-domain ESD solution is needed that complies with the Human Body Model ESD values (2kV) as well as the IC voltage levels. The proposal aims to create a custom multi-domain on-chip ESD IP in a TSMCs 65nm CMOS technology using circuit-device-system co-design. A custom ESD design based on diode chain is proposed via the failure analysis from device physics based TCAD simulations. Calibrated device simulations will analyse ESD failure informing the design of new ESD designs to be tested at the circuit level and sent further for chip fabrication on TSMCs 65nm CMOS technology. The initial work shows the potential of the proposed ESD design approach for high-voltage stimulators. Finally, the on-chip ESD designs will be tested against the human body model (2kV) ESD levels for failure to evaluate performance. This compact, physics-based ESD IP design will benefit the implantable biomedical field, supporting future neurostimulator and pacemaker IP development. This ESD IP can also serve as a foundational block for On-chip/Off-chip ESD protection across India’s biomedical IP industry. This methodology enhances chip area efficiency while maintaining strong ESD protection, applicable in both academic and industrial settings. In the short term, a live demonstration of this ESD solution can support researchers developing stimulator ICs. The project aligns with India's current focus on electronics manufacturing, supported by the Chips to Startup (C2S) program.