×

img Acces sibility Controls

Research Projects Banner

Research Projects

High voltage & ESD device development & enablement for SCL 180nm CMOS Technology

Implementing Organization

Indian Institute of Science
Principal Investigator
Dr. Mayank Shrivastava
Assistant Professor
|
Indian Institute of Science
Department of Electronic Systems Engineering

Project Overview

Drain extended MOS (DeMOS / LDMOS) and ESD protection devices are the key enablers of advance ASICs or System on Chips (SoCs), which allows systems scaling for a range of commercial and strategic products. LDMOS devices enable high voltage circuit operation over the same chip, whereas ESD devices protect ICs from unwanted ESD related failure. SCL’s mandate to feed to the SoC needs of ISRO and other strategic sectors is largely hindered due to unavailability of LDMOS and ESD devices in SCL’s CMOS line. Through this collaborative project IISc will develop 6 different DeMOS devices for integrated high voltage circuit applications, 2 ESD protection devices and will enable it in SCL’s 180nm CMOS line. Device design, simulation, characterization, reliability and device enablement will be taken care by IISc, whereas SCL’s role is to run process lots as per the process/mask details and detailed design of experiments developed by IISc.
Funding Organization
Funding Organization
Department of Science and Technology (DST)
Quick Information
Area of Research
Engineering Sciences
Focus Area
Methodology for implementation Pedagogy Security
Sanction Amount
₹ 2.98 Cr
Status
Ongoing
Output
No. of Research Paper
00
Technologies (If Any)
00
No. of PhD Produced
N/A
Startup (If Any)
00
No. of Patents
Filed :00
Grant :00
arrowtop