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Power Aware Compiler for Embedded Processors

Implementing Organization

Indian Institute of Information Technology Allahabad
Indian Institute of Technology (IIT)
Principal Investigator
Dr. Bibhas Ghoshal
Assistant Professor
|
Indian Institute of Information Technology Allahabad
Department of Information & Technology
CO-Principal Investigator
Prof. Indranil Sengupta
Professor
|
Department of Mechanical Engineering, Indian Institute of Technology (IIT), Kharagpur, West Bengal

Project Overview

As embedded systems are becoming more computationally intensive, power consumption has gained importance vis-a-vis performance. Software based control of different components in embedded devices has paved the way for development of compilation and operating strategies to reduce power dissipation in these devices. However, research suggests that majority of low power optimization techniques have been by-product of performance optimizations. In this work, we wish to explore different compiler based optimization techniques specifically targeting low power embedded devices and then develop these techniques as libraries which can be integrated in any compilation flow for embedded systems. Next, each of the considered technique would be evaluated for its benefit by performing physical measurements on different target systems for a set of representative benchmarks. Finally, we plan to integrate the developed libraries in LLVM compiler infrastructure framework to provide a complete power aware compiler solution for embedded devices.
Funding Organization
Funding Organization
Indian Institute of Information Technology Allahabad
Quick Information
Area of Research
Computer Sciences and Information Technology
Focus Area
CAD for Reliability and Safety, ICT Tools for Healthcare and Assistive Technology, Industrial and Medical Internet of Things, Smart City
Sanction Amount
₹ 40.46 L
Status
Ongoing
Output
No. of Research Paper
00
Technologies (If Any)
00
No. of PhD Produced
N/A
Startup (If Any)
00
No. of Patents
Filed :00
Grant :00
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