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Modeling of high voltage (10-20, 40-60V) N /P LDMOS devices developed at SCL in 180nm CMOS baseline process technology

Implementing Organization

Semi Conductor Laboratory (SCL), Chandigarh
CO-Principal Investigator
Shri Amit Kumar Singh
Semi Conductor Laboratory (SCL), Chandigarh
CO-Principal Investigator
Shri Saahil Singla
Semi Conductor Laboratory (SCL), Chandigarh

Project Overview

Process development work at SCL is inprogress for the process integration of LDMOS(VDS: 10-20, 40-60V; VGS: 3.3-5V) devices (nand PMOS) in standard 180nm baselineprocess. Once the devices are enabled, SPICE device models are required for theabove LDMOS devices for circuit designimplementation. The developed models shouldbe accurately predicting both DC and ACperformance of the devices over a range ofvoltage, temperatures (-55 to 125°C) andfrequencies.

Related Research

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Funding Organization
Funding Organization
Department of Space (DoS)
Quick Information
Area of Research
Astronomy & Space Sciences
Focus Area
Semiconductor Device Modeling
Status
Ongoing
Output
No. of Research Paper
00
Technologies (If Any)
00
No. of PhD Produced
N/A
Startup (If Any)
00
No. of Patents
Filed :00
Grant :00
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