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Modeling of devices (SPICE based) (in partially depleted SOI-CMOS process and PDSOI analog cell library considering floating-body effect (FB) and self-heating effect

Implementing Organization

Semi Conductor Laboratory (SCL), Chandigarh
CO-Principal Investigator
Shri HS Jatana
Semi Conductor Laboratory (SCL), Chandigarh
CO-Principal Investigator
Shri Avinash Singh
Semi Conductor Laboratory (SCL), Chandigarh

About

Partially depleted SOI-CMOS process has beensuccessfully integrated with floating body MOSFETperformance close to Bulk CMOS. MOSFETs withdifferent body connection schemes (I, T and Htype) are also fabricated and characterized. Theprocess is projected to be used for Radhard, lowpowerand RF applications.

Related Research

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Funding Organization
Funding Organization
Department of Space (DoS)
Quick Information
Area of Research
Astronomy & Space Sciences
Focus Area
Partially Depleted SOI-CMOS process development in 180nm
Status
Ongoing
Contact
gh_dpg@scl.gov.in
Output
No. of Research Paper
00
Technologies (If Any)
00
No. of PhD Produced
00
No. of Patents
Filed : 00
Grant : 00
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