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Design of PLL with VCO, 40MHz -1000MHz, Ultra low phase noise -110dBc/Hz, very low RMS jitter<180fs

Implementing Organization

Semi Conductor Laboratory (SCL), Chandigarh
CO-Principal Investigator
HS Jatana
Semi Conductor Laboratory (SCL), Chandigarh
CO-Principal Investigator
Ashutosh Yadav
Semi Conductor Laboratory (SCL), Chandigarh

About

The aim is to design a PLL which could beused in various circuits as embedded blockand as standalone device.The PLL must generate clock rates in therange 40 –1000 MHz range with very low RMS jitter.

Related Research

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Funding Organization
Funding Organization
Department of Space (DoS)
Quick Information
Area of Research
Astronomy & Space Sciences
Focus Area
VLSI Design
Status
Ongoing
Contact
gh_dpg@scl.gov.in
Output
No. of Research Paper
00
Technologies (If Any)
00
No. of PhD Produced
00
No. of Patents
Filed : 00
Grant : 00
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