Research Projects

Design of SAR ADC 14/16 bit, 20/10 Mbps, lowpower (<300mW), 3.3V supply in 180nm SCL technology: The successive-approximation ADC is by far the most popular architecture for at a acquisition applications. Successive approximation ADCs comprise four main subcircuits: the sample-and-hold amplifier (SHA), Analog comparator, reference digital-to-Analog converter (DAC), and successiveapproximation register (SAR). Because the SAR controls the converter’s operation, successive-approximation converters are often called SAR ADCs. This SAR ADC should cater test and Measurement, Imaging and high-Precision, high-Speed data acquisition applications with these features in Junction temperature range -40 °C to+125 °CSNDR >72 dBFS at 10 Msps SFDR >80 dBc at 10 Msps DNL <±0.5LSBINL <±0.5LSB No missing Code Gain Error<±0.5LSB Offset Error<±0.5LSB Output data format in LVDS or CMOS.