Explorative co-design approach and innovative solutions to address performance and reliability challenges in e-mode gallium nitride high electron mobility power transistors
Implementing Organization
Indian Institute of Science
Principal Investigator
Prof. Mayank Shrivastava
Associate Professor
|
Indian Institute of Science
About
This project will attempt to address the following science and technology gaps related to e-mode GaN HEMT technology with a goal to address the root cause of performance and reliability rate limiters and demonstrate high performance – high-reliability e-mode GaN HEMTs:
(a) Missing co-design approach to holistically investigate various phenomena as a function of material, process, and design, with a goal to push performance and reliability limits.
(b) Performance and reliability exploration of novel/hybrid gate stacks.
(c) The interplay between GaN buffer, AlGaN surface, field plate design, surface passivation, gate stack, e-field localisation and hot carrier/breakdown behaviour affecting reliability and dynamic RON behaviour.
(d) Transient self-heating behaviour of GaN HEMTs (heat conduction through epi-stack, contacts, 2DEG, etc.).
(e) Electric field localisation and methods to engineer e-field to mitigate hot carrier issues and early failure.
(f) Role of traps in governing time-dependent dielectric breakdown in GaN buffer triggered by accumulated piezo-electric stress.
(g) Impact of process and device design on vertical stress-driven lateral device degradation and failure.
(h) Physics of Dynamic RON and impact of device design as well as gate stack process parameters.
(i) Impact of process and design on inverse piezoelectric effect which originates from field-induced mechanical stress and leads to the creation of crystallographic defects due to unwanted e-field localisation.
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