Research Projects

Display backplanes consist of transistors that control current flow to individual pixels, using positive capacitance from the dielectric layer. High permittivity dielectrics like hafnium oxide are used to achieve the same modulation in current. Displays require a voltage range of 5-20 V, but further reduction in these voltages leads to more power-efficient displays. The semiconducting channel is typically amorphous silicon, but recent displays use Indium Gallium Zinc Oxide (a-IGZO), which shows high field effect mobilities. To reduce power consumption, steep switching transistors with negative capacitance NC effect are proposed. The integration of a-IGZO semiconducting layer with doped-HfO2 ferroelectrics is also explored. The fabrication and characterization of NCFET arrays for display backplanes are optimized for ultralow power reliable operation. This project contributes to the India Semiconductor Mission and helps build an ecosystem of ultralow power display technologies in India.