Research Projects

Clocking in modern SoCs is typically achieved through multiple phase-locked loops (PLL) operating on a clean reference. However, fractional division-based open-loop clock synthesizers offer a promising alternative, resulting in significant area and power savings. This is achieved through an integer divider, which is switched between integers by a control logic based on a frequency control word. The output has deterministic jitter, resulting in unwanted fractional spurs. This spur is reduced by re-timing the output clock edges using a digital-to-time converter (DTC). Open-loop architectures are suitable for clocking with spread spectrum or dynamic frequency scaling requirements. Optimizing these open-loop clock synthesizers for power efficiency will enable compact and low power clocking architectures, benefiting all modern SoCs. A three-pronged approach will be followed to improve the performance of fractional division-based clock synthesizers. The first step is to explore low-power calibration algorithms that can suppress the fractional spur and a compatible divider architecture. The second step is to explore a suitable DTC architecture for open-loop clock synthesis in terms of linearity, jitter, and power consumption. The proposed architecture will be designed and implemented in a 65nm technology node, with the efficacy demonstrated through measurements from a prototype chip.