Research Projects

The miniaturization of electronics has led to the development of cryogenic CMOS (cryo-CMOS) based quantum computers, which have the potential to significantly speed up computations compared to traditional supercomputers. These quantum computers operate at cryogenic temperatures, where qubits remain coherent for a short period, allowing them to process millions of qubits simultaneously. However, the noise and bandwidth of these loops can significantly impact the system's scalability and compactness. To improve performance metrics, cryogenic CMOS can be used in fault-tolerant loops for reliable qubit readouts. However, scaling conventional CMOS can lead to severe short channel effects (SCEs), deteriorating device performance. To address this, cryo-CMOS computing requires a new set of CMOS devices and improved scalability, design embedding, and verification. The physical and quantum transport properties of the NSFET can be explored at cryogenic temperatures (77K to 4mK) to create a potential successor to conventional cryo-CMOS. Accurate modeling of the cryo-Nanosheet transistor (cryo-NSFET) is also essential for circuit simulations, such as the design and implementation of analog front-end readout circuitry. The proposed proposal will analyze the NSFET for cryogenic temperatures down to mK and elaborate on the physical modeling equations of cryo-NSFETs, including quantum transport equations, scattering mechanisms, trap analysis, and more. The artificial neural network (ANN) approach will be employed to create an extensive data set for realizing the Verilog-A model for implementing analog front-end readout circuitry for cryo-Nanosheet.