Research Projects

The increasing use of FPGA boards for payload applications in nano-satellites and re-programmable payloads has led to a need for defect-tolerant FPGA boards. However, commercially available FPGA boards are limited and costly, focusing on soft-errors rather than permanent defects or defects due to ageing. In radiation-prone environments, highly energized particles can cause electronics charges to accumulate and excess electrical transient pule, known as single event transient (sET), which may cause bit-flip in memory elements. Aggressive process scaling in the modern age reduces supply voltage and node capacitance, making nanoscale CMOs circuits susceptible to failures. Ultra-low power design is crucial for space applications due to limited energy sources restricting the size and weight of batteries and power supplies. This project aims to develop fault-tolerant FPGA structures for payload applications in nano-satellites, considering all types of permanent and transient defects, including single event effects (sEEs). The area-saving dynamic reconfiguration method will be hot-standby and C-testable, detecting and tolerating faults in real-time with minimal complexity. static masking methods will be optimized for resource-constrained nano-satellites, and low-power designs of memory elements will be hardened to soft-errors. The controller in the processing element and payloads of the nano-satellite will also be made tolerant to probable defects, ensuring accurate work without failure. A half-access scheme will provide a low-power solution for controller design.