Research Projects

Multi-Processor Systems-on-Chip (MPSoCs) are crucial for high-performance computing applications in various domains such as robotics, machine vision, artificial intelligence, animation, image processing, mobile computing, IoTs, telemetry, edge computing, ambient intelligence, and biomedical engineering. Technology scaling, which miniaturizes on-chip transistor sizes, allows for the integration of more processing elements (PEs) on a single MPSoC, resulting in performance improvements. However, technology scaling also increases the volume of on-chip data to be communicated among different processing elements. Network-on-Chip (NoC) has emerged as a potential scalable and reusable on-chip interconnect solution to support this large volume of communication. Despite NoCs efficiently handling communication requirements of MPSoCs, the ever-increasing power-density due to continuous technology scaling is yet to be managed. Power density in MPSoCs has reached 50Watt/cm² at 100nm technology node and almost doubles in every two years with advancements in technology. High temperature increases RC-delays, leakage power consumption, transistor-speed, static noise margin, and reliability of the NoC. Three-dimensional Networks-on-Chip (3D-NoCs) have become a hot domain of research due to increased packing density and improved Average Packet Latency and Throughput. However, increasing Si-layer distance from the heat sink increases thermal resistance, making temperature control a primary design requirement in 3D-NoCs. This project proposes thermal-aware task mapping in Regular 3D-NoCs (RMNoCs) and thermal-aware topology synthesis in Application-Specific 3D-NoCs.

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