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Wafer-scale integration and interfacial engineering of 2D van der Walls superlattice for next-generation nano-scale devices

Implementing Organization

Indian Institute Of Technology (IITBHU), Uttar Pradesh
Principal Investigator
Dr. Santanu Das
Indian Institute Of Technology (IITBHU), Uttar Pradesh

Project Overview

The advancements in two-dimensional (2D) transition metal dichalcogenides (TMDs) materials have led to the introduction of new 2D van der Waals (vdW) superlattice-based multi-junction devices. These devices exhibit exceptional performance, including high on/off ratio, high responsivity, faster detectivity, excellent heat dissipation, remarkable mechanical properties, and outstanding stability. These atomically thin 2D materials have immense potential for developing multi-junction device arrays with a large device-to-device consistency. The heterojunction formed by different 2D semiconductor materials plays a crucial role in promoting state-of-the-art optoelectronic materials, which possess the vital building blocks for manufacturing and integrating next-generation optoelectronic/sensor devices with Si-technology. The researchers propose developing various state-of-the-art processes for surface engineering of 2D vdW heterostructures/superlattice growth and integrating them with Silicon-technology. This includes controlling atomic-scale defects, defect chemistry, and defect alignment over large areas to understand the formation of mesoscopic boundaries like surfaces or interfaces. The researchers also propose developing chemical vapor deposition (CVD) synthesis processes to enforce defect control, superlattice formation, site-specific nucleation, and domain-aligned growth through various thermodynamic laws of defects and disorders. The aim is to develop optoelectronic-grade 2D-vdW heterostructures followed by fabrication of optoelectronic devices, including optical sensors, photodetectors, and quantum tunneling transistors, and understand their critical limits for integrating devices with various Si-based substrates. Exploring device performance could open up enormous possibilities for discovering novel technological findings to combine with Si-based electronic chip/circuit manufacturing.
Funding Organization
Funding Organization
Science and Engineering Research Board (SERB), New Delhi
Anusandhan National Research Foundation (ANRF)
Quick Information
Area of Research
Physical Sciences
Start Year
2023
End Year
2026
Sanction Amount
₹ 38.88 L
Status
Ongoing
Output
No. of Research Paper
00
Technologies (If Any)
00
No. of PhD Produced
N/A
Startup (If Any)
00
No. of Patents
Filed :01
Grant :00
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