Research Projects

Side-Channel attacks cause major problems in multi-core architectures as the last-level-cache is shared among several cores. In side-channel attacks, hardware footprints such as memory accesses, execution time, and power consumption are analysed to infer vital information. Memory access patterns may be inferred by monitoring the cache lines in the shared cache. Dynamic partitioning of cache in multi-core architectures increases the vulnerability [1]. With the increasing demand and complexity in Network-on-Chip (NoC) designs, Data snooping is a major concern, due to third-party NoC IPs, untrusted hardware and software components. Maliciously inserted HardwareTrojans (HTs) into NoC IPs, such as the network interface (NI) and the NoC router are the major contributors for data snooping attacks [2]. Preventing security threats while employing multi-core processors when used in safety-critical, aerospace and defense applications is even more critical. Scheduling, Separation or Virtualization, Design space exploration are some of the techniques employed to provide security in multi-core architectures [1-5]. This proposals aims to focus on enhancing the security features in multi-core architectures using the combination of the above mentioned techniques.