Assistant Professor, Electronics and Communication Engineering, National Institute of Technology (NIT) Rourkela, Odisha
CO-Principal Investigator
Shri Ranganath KP
ISRO Inertial Systems Unit (IISU), ISRO, Thiruvananthapuram, Kerala
Project Overview
For all precision sensors, it is required to acquire the data accurately using precision data converters, process the acquired data for the sensor control and compensation requirement and then give the data back to the sensor for closed loop application. The project aims to design and develop a mixed signal SOC with 100MHz operating rate in VHDL/Verilog code. The developed processor core has to be compatible to RISC-V 32 and has to work with certified compiler chain available to RISC-V. The configurability to add any peripheral to the bus for the future requirement to be present in the processor core design. The Design planned to be implemented in SCL-180nm technology node with 100MHz frequency and has to provide suitable time margins for operating in this frequency.
Achievements
The project being undertaken by ISRO in collaboration with academia is directly or indirectly beneficial to the society.
Source
Source
Indian Space Research Organisation (ISRO)- Department of Space (DOS) 2022-2053
Assistant Professor, Electronics and Communication Engineering, National Institute of Technology (NIT) Rourkela, Odisha
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