Design of PLL with VCO, 40MHz -1000MHz, Ultra low phase noise -110dBc/Hz, very low RMS jitter<180fs

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Implementing Organization

Semi Conductor Laboratory (SCL), Chandigarh

Principal Investigator

NULL

CO-Principal Investigator

HS Jatana

Semi Conductor Laboratory (SCL), Chandigarh, Ashutosh Yadav, Semi Conductor Laboratory (SCL), Chandigarh

Project Overview

The aim is to design a PLL which could beused in various circuits as embedded blockand as standalone device.The PLL must generate clock rates in therange 40 –1000 MHz range with very low RMS jitter.

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Funding Organization

Department of Space (DoS)

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Area of Research

Astronomy & Space Sciences

Focus Area

VLSI Design

Status

ongoing

Contact

gh_dpg@scl.gov.in

Output

No. of Research Paper

Technologies (If Any)

No. of PhD Produced

Publications

No. of Patents

Filed : 00

Grant : 00

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