The project envisages to develop hardware efficient architecture of CCSDS 122.1 standard and implement the RTL on Xilinx Kintex Ultrascale XCKU040 Space-Grade FPGA. Various RTL blocks such as Integer Wavelet Transform (IWT), the Pairwise Orthogonal Transform (POT), Karhunen Loeve transform (KLT) will be used in the spectral transform process and the Float DWT (Discrete Wavelet Transform) will be optimized for low power and high speed image processing.
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