Development of Signal
Processing Chip for
GNSS Anti-jamming
functionality
Implementing Organization
Department Of Physics, Indian Institute of Technology (IIT) Delhi
Project Overview
The aim of the project is to integerate 16 BIT ADC with 86Db SFDR (along with VGA and LDO) with RF interefernce mitigating module.This combined design will be back end design and will be fabricated under this project to deliver GNSS signal processing chip for GNSS Anti jamming functionality
Department Of Physics, Indian Institute of Technology (IIT) Delhi
Acces sibility Controls