Research Projects

Modern processors use multi-core architecture with a multi-level cache hierarchy to meet the demands of high-performance computing. Each processor core has its own private cache, and the Last Level cache (LLC) is shared by all. Traditional SRAM technologies are used to design cache memories, but non-volatile memory (NVM) technologies, particularly STTRAM, have recently been used in the design of LLC. However, LLCs have become a popular target for cache timing channel attacks due to their shared nature and high density. Randomisation and partitioning are defense techniques against these attacks. Randomisation techniques eliminate fixed address to cache-set mapping, while partitioning isolates applications to prevent cross-core conflict. Over the last two decades, many cache content management policies have been proposed to improve cache memory performance, including replacement policies and write management policies. However, these policies provide no performance benefit in secure processors. When combined with recent replacement algorithms, randomisation and partition-based countermeasures reduce system performance below that achievable with the Least Recently Used (LRU) replacement policy. This proposal addresses the challenges that future generation processors will face in terms of security and performance efficiency. The processor manufacturers have not yet faced these issues, as the recent and optimized cache content management policies are yet to be implemented in the actual chip. Any attempt to use these policies in secure processors will face the issues raised by this proposal.